ESD is a threat to IC reliability. Introduction of new materials in IC fabrication and the scaling of critical transistor interconnect dimensions and dielectrics have increased a circuit's susceptibility to ESD events and degraded the capability to safely dissipate ESD charge. This technological trend poses even greater challenges for design of effective protection structures and circuit topologies. The need to reduce parasitic capacitance on high speed input/output lines of an IC chip (i.e., I/Os), as well as the need to reduce chip area consumed by ESD protection circuits pose further challenges. Leakage currents associated with conventional ESD protection devices during normal operation (i.e., when there is no ESD event) is another significant problem for sub 32 nm technology nodes.
ESD protection devices in the art may be divided into two general categories: snapback devices and non-snapback devices. The most typical non-snapback devices are p-n junction diodes usually arranged in a dual diode configuration where two diodes (P+/n and N+/p) are connected back to back and the pair further connected to an exposed I/O pin or pad. During an ESD event the diodes sink current so as to protect the I/O device and internal circuitry of the IC chip from damage, such as gate oxide breakdown, source-drain shorts, interlayer dielectric (ILD) breakdown, etc. The most typical snapback devices are transistor based, primarily MOSFETs. While snapback devices usually have relatively smaller size and lower parasitic capacitance than non-snapback implementations, “off-state” source-drain leakage current is a bigger problem for MOSFET-based designs, particularly at the 22 nm CMOS technology node. An ESD protection snapback device which can conduct higher current (during ESD event) and provide lower leakage current (during normal operation) is therefore needed for 22 nm CMOS technology node and beyond.